基于顺序等效采样的DAC测试方法设计
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TN45

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Design of DAC test based on sequential equivalent sampling
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    摘要:

    当前数模转换器(DAC) 测试面临不能兼顾采样精度与采样速率的问题,测试时通常只能二者选其一,随着 DAC器件 的发展,常规测试系统不能满足当前测试领域需求。针对采样速率提升导致系统噪声提高,最终使采样系统有效分辨率恶化 的问题,在分析对比了当前采样技术和系统噪声影响的基础上,提出了基于顺序等效采样的DAC 测试方法。该方法将高频 的原始信号在时间域上展开,其核心是制造采样周期与输入信号的周期的固定频差以进行分周期采样。对采样时钟抖动对 系统有效位数的影响进行分析,确定了系统的最大时钟抖动,根据被测信号周期特征设计了测试系统的采样结构与周期。并 对一款16 bit,500 MHz输出的DAC 进行了测试,其结果与传统外挂频谱仪的测试结果进行对比。对比结果表明两次实验获 得的频谱特征一致,采用本文设计的测试系统获得的测试结果得到了约4dBc 无杂散范围提升,约3 dBc 双音交调参数提升, 证明基于顺序等效采样DAC测试方法的有效性。

    Abstract:

    With the rapid development of digital-to-analog converters(DAC),high sampling accuracy and high sampling rate cannot be achieved simultaneously in DAC testing.A DAC test design method based on sequential equivalent sampling is proposed to solve the problem of effective resolution deterioration,which caused by noise increase due to sampling rate increase.The method expands the high-frequency original signal in time domain,and samples expanded signal with uniform period.The key is to generate fixed frequency difference between the period of sampling clock and the period of input signal.In addition,this paper analyzes the influence of sampling clock jitter on the effective-number-of- bits(ENOB)of the system,determines the maximum clockjitter of the system,and designs the sampling structure and period of the test system according to the periodic characteristics of the tested signal.A16 Bit,500 MHz output DAC is tested by this method and the results are compared with traditional method by external spectrometer.The results show that the spectral characteristics obtained in the two experiments are consistent,and the proposed method achieves about 4 dBc improvement in Spurious-free dynamic range(SFDR)and about 3 dBc improvement in Two-tone intermodulation distortion(IMD)parameters,which proves the effectiveness of the sequential equivalent sampling DAC test method.

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寿开元,解维坤,季伟伟,张凯虹,宋国栋.基于顺序等效采样的DAC测试方法设计[J].国外电子测量技术,2024,43(9):104-110

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  • 在线发布日期: 2024-12-13
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