The reading of largescale acquiring data will consume long time. Especially, while single period to read data is chosen, microprocessor interface of PCI bus will influence realtime dealing of acquiring data seriously. In this paper, PCI interface controller and DDR controller is designed in FPGA and the protocol of PCI bus transformed to userdefined local bus of interior. The double interface FIFO is taken as the control buffer of clock synchronization, which used to synchrony local bus of interior and DDR controller. Thereby, the problem of clock synchronization is solved between microprocessor and DDR memory and the rapid uploading of largescale acquiring data is realized.