1.中国电子科技集团公司第四十一研究所 蚌埠 233006;2.电子信息测试技术安徽省重点实验室 蚌埠 233006
TN2
1.The 41st Institute of China Electronics Technology Group Corporation, Bengbu 233006, China;2.Key Laboratory of Electronic Measurement Technology, Bengbu 233006, China
针对大规模采集数据读取时间较长的问题，特别是PCI总线接口的微处理器，采用单周期读取方式时，将会严重影响采集数据的实时处理。通过在FPGA中设计PCI接口控制器和DDR控制器，将PCI总线接口协议转换到内部自定义局部总线，采用双端口FIFO 作为时序同步控制缓冲器，同步内部局部总线和DDR控制器，从而解决了微处理器对DDR存储器突发读取的时序同步问题，实现了大规模采集数据的快速上传。
The reading of largescale acquiring data will consume long time. Especially, while single period to read data is chosen, microprocessor interface of PCI bus will influence realtime dealing of acquiring data seriously. In this paper, PCI interface controller and DDR controller is designed in FPGA and the protocol of PCI bus transformed to userdefined local bus of interior. The double interface FIFO is taken as the control buffer of clock synchronization, which used to synchrony local bus of interior and DDR controller. Thereby, the problem of clock synchronization is solved between microprocessor and DDR memory and the rapid uploading of largescale acquiring data is realized.
栗永强,张永坡,布乃红.基于FPGA的DDR存储器突发读取设计技术[J].国外电子测量技术,2016,35(6):51-54
复制
