The logic synthesis stage and physical synthesis stage will be repeated several times, when mapping the logic circuits to FPGA, to meet the area and timing constraints. In order to accelerate the traditional FPGA CAD flow, this paper presents a feed-forward neural network to predict the area and delay before the physical synthesis stage. Compared to the placement and routing results from VTR7.0, the mean relative error（MRE） of the predicted area is 4.9%, and the mean relative error（MRE）of the predicted delay is 6.4%.This method works at early stage, but acquires a high accuracy compared to the related work. The estimator will help the designer reduce the design cycle and be capable of fully exploring the design space during the logic synthesis stage, thus improving the whole design quality.