With the increase of data transmission speed, distance and reliability requirements, and considering the safety of workers in the test environment, a design scheme of DC balancing technology based on LVDS is proposed in this paper. In this scheme, LVDS serializer SN65LV1023A and SN65LV1224B are used as sending and receiving chips. Due to the limitations of LVDS in long-distance transmission, Therefore, the driver LMH0002TMA and equalizer LMH0024MA are used in the hardware design to increase the driving capacity of the signal and compensate the signal attenuation. The isolator ADN4651 and RCLamp3324P chips are added to the peripheral circuit to provide signal isolation and protection and ESD protection for the high-speed data interface. At the same time, in the software design, 8B/10B coding technology is added to the core controller FPGA to ensure the DC balance in data transmission, that is, the continuous "1"/" 0 "in the data stream reaches a balanced and even state, reduces the bit error rate and improves the reliability of the data. After a large number of experimental tests, this design can be transmitted on 90m twisted pair at a rate of 300Mbit/s with zero error.