Aiming at the requirements of high-speed broadband wireless communication systems, the existing discrete Fourier transform extended orthogonal frequency division multiplexing implementation methods have limitations in resource utilization and calculation speed. To solve these issues, this paper proposes an optimization approach that combines the Cooley-Tukey algorithm with the Winograd Fourier Transform Algorithm (WFTA). Arithmetic optimizations were applied to reduce the use of multipliers, enabling the optimization of the radix-2 DIT butterfly structure for a 1024-point FFT. Additionally, the WFTA algorithm was introduced, using shift-based simplifications to optimize resource allocation for 3-point DFTs. FPGA resources were designed and optimized, resulting in the successful implementation of a 3072-point FFT on an FPGA. The results of FPGA simulation and platform test show that, compared to the Xilinx LTE FFT IP core, the proposed optimization reduced multiplier resource consumption by 24.96% and increased processing speed by 14.07%. Moreover, this algorithm significantly reduced the computational complexity of the FFT, greatly enhancing the overall performance of DFT in DFT-S-OFDM system. In summary, the optimization proposed in this paper provides an efficient solution for implementing DFT-S-OFDM technology in practical communication systems.