In order to reduce the volume and the cost of the function signal generator, a design proposal of function signal generator based on Nios II has been proposed. By using Verilog HDL, this proposal can design hardware bottom module and embed Nios II soft core processor in the FPGA (field programmable gate array) chip as the control core of the system. What’s more, this proposal generates the function signals by the mode of software and hardware combination with DDS Technology. It turned out by the test that this kind of proposal worked well. It can not only achieve the purpose of reducing the volume and the cost, but also generate a variety of function signals with stable waveform and adjustable amplitude. The system has good scalability and favorable prospects for development.