In order to meet the requirements of the special timing signal in the test section, a configurable timing signal generation system is designed to realize the output of the multichannel timing signal. The signal generating system consists of two parts: the host computer and the slave computer. The host computer software is used to configure the output timing, and the slave computer using hardware structure through combination of STM32+FPGA. As the STM32 chip of the slave computer and FPGA using two different clocks, so the design uses asynchronous FIFO in the FPGA chip to achieve data communication to STM32, which can achieve effectively the parallel data transmission between the two.